In recent years, SMP (Symmetric Multiprocessing) has been widely used for faster processing. The SMP is intended to share and manage a physical memory, and provide a cache in a DRAM to perform cache control by LRU (Least Recently Used) method (LRU control), for example.
On the LRU control, each of cores in a CPU (central processing unit) connects a management block for a cache page used in a process to the tail end of an LRU link. The LRU link is a queue structure in which each of management blocks has the IDs of management blocks connected before and after the management block to hold a link relationship. Thus, each of the management blocks is connected to the LRU link by reading the management block pointed to by an MRU (Most Recently Used) pointer and updating the IDs of the management blocks connected before and after the pointed management block.
When the management block pointed to by the MRU pointer is saved in a CPU cache (local cache), each of the cores reads the management block pointed to by the MRU pointer from the CPU cache. This process is called CPU cache hit, which allows each of the cores to reconnect the management blocks to the link at faster speeds.
Japanese Laid-open Patent Publication No. 2006-99802
Japanese Laid-open Patent Publication No. 2007-334752
On the other hand, when the management block pointed to by the MRU pointer is not saved in the CPU cache, each of the cores needs to read the management block pointed to by the MRU pointer from the DRAM cache, which results in deterioration of processing performance.
When the cores perform processes in parallel, the management blocks for cache pages used in the process performed by one core are not necessarily connected to the LRU link in a consecutive manner. In addition, the probability that such management blocks are consecutively connected to the LRU link becomes lower with increase in the number of cores. In light of recent years' trend toward increase in the number of cores, the problem with failure of CPU cache hit tends to be more prominent.